The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such\nas Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical\nproperties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx\nXC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the\nreconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To\ndemonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo p-estimator for the\nCray XD1. The RC Monte Carlo p-estimator shows a 19.1Ã?â?? speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1.\nIn this paper we describe the FPGA implementation for HASPRNG and a p-estimator example application exploiting the finegrained\nparallelism and mathematical properties of the SPRNG algorithm.
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